The present invention relates to a method for manufacturing a semiconductor device and more particularly, to a method and system for accurately detecting and correcting an overlay error in a light exposure step.
A semiconductor device manufactured by repeating for each layer a step of depositing a conductive or insulating film on a wafer and a lithography step of coating a resist as a photosensitive agent on the film, subjecting the resist to light exposure with a circuit pattern on a reticle disposed therebetween, developing it and etching the film with use of the remaining resist as a mask to thereby form the circuit pattern on the wafer. At this time, when the circuit pattern during the exposure is positionally shifted (has a registration error) to a pattern of an underlying layer, the circuit is disconnected or short-circuited, which results in that a resulting semiconductor device becomes faulty. To avoid this, prior to the exposure of the circuit pattern, the exposure apparatus optically detects alignment marks provided in an outer periphery of the circuit pattern as an underlying layer, measures the position of the underlying layer, and corrects the transfer position to thereby realize alignment between the underlying layer and exposure layer.
Further, after actual exposure and transfer (prior to etching), an overlay inspection equipment measures a relative registration error between the overlay mark of the underlying layer and the overlay mark of the exposure layer, and feeds the registration error back to the exposure apparatus as a correction. When the registration error exceeds its allowable value, the exposure apparatus, after stripping the resist, performs re-coating, light exposing and developing operations. Such work is called re-work. That is, the overlay inspection is carried out for the purpose of judging necessity or non-necessity of the feedback to the exposure apparatus and re-work.
It is assumed in the above alignment inspection that the registration error measured based on the overlay mark indicates the registration error of the circuit pattern. However, now that, as the circuit pattern is made finer, the shift allowable value is made smaller, it has been found that there sometimes occurs such a situation that the above fact cannot hold true. The registration error depends on the wave aberration of an exposure lens. This will be explained below by referring to FIG. 18.
An exposure lens 30, for example, has a coma aberration 300 as the wave aberration. This is asymmetrical aberration resulting, for example, from image 2140 of the entire line pattern. Thus, when one end of the line pattern becomes asymmetrical, an error xcex94ER may be generated in the measured registration error.
It is therefore and object of the present invention to provide a semiconductor manufacturing method for correcting a difference in registration error between a circuit pattern and an overlay mark while eliminating the need for modifying the overlay mark to a fine line pattern. Novel features of the present invention will become clear from the description of the present specification and attached drawings.
Some aspects of inventions disclosed in the present application are as follows.
There is provided a method of manufacturing a semiconductor device, which includes the steps of measuring an actual registration error between a transfer image when a first overlay mark formed on a first reticle is actually formed as transferred on a substrate with use of a first aligner or exposure equipment and a transfer image when a second overlay mark formed on a second reticle is formed as transferred on the substrate, predicting an actual registration error between the transfer images of the circuit patterns from data of the measured registration error by use of a previously determined relationship between a registration error between a transfer image formed when a first circuit pattern formed on the first reticle is transferred to the substrate by use of the first exposure equipment and a registration error between a transfer image formed when a second circuit pattern formed on the second reticle is transferred to the substrate by use of the second aligner or exposure equipment and also with use of the registration error between the transfer images of the overlay marks, correcting the second exposure device on the basis of the predicted registration error information between the transfer images of the circuit patterns, and subjecting the second circuit pattern subjected by the first exposure equipment to light exposure by the corrected second exposure equipment to light exposure.
As a result, the system can accurately predict the registration error of the circuit pattern from the measured value of the registration error of the overlay mark, can set a suitable correction value for the exposure equipment, and can increase the yield of the semiconductor device.
Further, the circuit pattern is a circuit pattern having the severest tolerance of the overlay specifications. Since the system can set the correction value for the circuit pattern which has the severest tolerance of the overlay specification, the system can increase the yield when compared with a case of using a correction value determined from a circuit pattern which has the severest tolerance of the overlay specification.
There is provided an overlay control method for subjecting a circuit pattern in a second layer formation process to light exposure on a circuit pattern in a first layer formation process to manufacture a semiconductor, wherein an overlay error central control limit and upper and lower control limits are determined from an actual measurement data of a circuit pattern registration error and overlay mark registration error measured before the manufacturing.
As a result, the overlay error as abnormality generation in the circuit pattern can be detected, thus enabling quick abnormality analysis and measure.
There is provided a system for manufacturing a semiconductor device wherein a circuit pattern in a second layer formation process is subjected to light exposure on a circuit pattern in a first layer formation process. The system includes a history storage device for storing a history of an exposure equipment, illumination conditions and a reticle used for manufacturing of a substrate to be exposed; a reticle data storage device for storing a dimension of a circuit pattern of the reticle, a dimension of an overlay mark, a coordinate value of the circuit pattern and a coordinate value of the overlay mark; an the eccentricity and tilt of an element lens and the surface accuracy error of the lens surface at the time of assembling the exposure lens 30. The coma aberration 300 has a tilt large in the vicinity of the periphery of the exposure lens 30. A light beam passing through the exposure lens 30 is bent by an amount proportional to the tilt of the coma aberration 300. Meanwhile, the angle of the beam diffracted by a reticle varies with the spatial frequency of a transfer pattern. Accordingly when the spatial frequency of the transfer pattern varies, the position of the beam passing through the exposure lens 30 is changed, thus changing also the registration error. FIGS. 18A and 18B show diagrams when an exposure beam 2003 is directed into a rough pattern 210 and a fine pattern 220 respectively. Since a diffracted beam 2005 of the fine pattern 220 of FIG. 18B having a large diffraction angle passes through the exposure lens 30 closer to its periphery than that of the rough pattern 210 of FIG. 18A, a registration error xcex94xxe2x80x2 of FIG. 18B is larger than a registration error xcex94x of FIG. 18A. This means that, since the spatial frequency varies with the circuit pattern and overlay mark, the registration error during transfer also varies, which leads to the fact that the aforementioned overlay inspection assumption is not satisfied.
With respect to light exposure, in addition to such usual illumination as shown in FIG. 19A, there may be employed annular illumination as described in a literature entitled xe2x80x9cOptical Alliancexe2x80x9d, January, 1998, page 4. FIG. 19B shows a case of annular illumination. In the annular illumination, an illumination light flux 2002 has an annular section and has an effect of enhancing the contrast of the transfer pattern. As shown in FIG. 19B, a registration error xcex94Xxe2x80x2 of the transfer pattern of the light flux expanded outwards becomes larger than a registration error xcex94X of the usual illumination. This means that even illumination conditions also affects a difference in registration error between the circuit pattern and overlay mark.
In order to solve the above problem, there is disclosed a method for performing overlay inspection with use of an overlay mark as a pattern having a spatial frequency similar to a circuit pattern in JP-A-10-312958.
The above known art may have problems which follow. That is, to make to coincide with the spatial frequency of the circuit pattern, an overlay mark 214 includes such a pattern 215 of several lines as shown in FIG. 20. However, since the pattern is fine and long, a part of the line pattern in the vicinity of an end of the overlay mark may fall or may tend to become easily asymmetrical under the influences of halation or wave aberration from an adjacent part 41. A registration error with respect to the underlying layer is calculated by processing the waveform of an optical illumination conditions storage device for storing the exposure equipment and illumination conditions for each process; a wave aberration data storage device for storing wave aberration data for each exposure equipment and each pattern coordinate value; a registration error calculation device for calculating a circuit pattern registration error of a second layer formation process to a first layer formation process and an overlay mark registration error of the second layer formation process to the first layer formation process from the illumination conditions, the circuit pattern dimension, the overlay mark dimension and the wave aberration for each coordinate value; a registration error relationship calculation device for calculating a relationship between the circuit pattern registration error and the overlay mark registration error; a registration error relationship storage device for storing the registration error relationship, a name of the first layer formation process, a name of the second layer formation process, exposure equipments, illumination conditions and reticles used in the first and second layer formation processes; an overlay control limit storage device for storing an overlay control limit for each product and process; an overlay control limit conversion device for converting the overlay control limit from the registration error relationship; an overlay inspection data storage device for storing overlay inspection data; a correction calculating device for calculating a correction of the second exposure equipment from the registration error relationship and the overlay inspection data; a host computer for performing control of an entire semiconductor manufacturing apparatus and input and output of information; an input/output control device for performing transfer of information of the plurality of storage device, a plurality of calculation device, selection device and judgement device and transmitting a correction value calculated by a start device issued from the start device judging device and by the correction value calculation device or a correction value issued from a combination of the information storage device to the host computer; an exposure equipment; and an overlay inspection equipment.
According to the present system, upon manufacturing a semiconductor device, a relationship between the circuit pattern registration error and overlay mark registration error in first and second layer formation processes can be quickly extracted from a history of the substrate to be exposed, and abnormality detection in an overlay inspection and feedback of a correction to the exposure equipment can be quickly achieved.
These and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiment of the invention as illustrated in the accompanying drawings.